HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 51

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

Register Name
Status Register
Revision ID
Class Code
Header Type
BIST
I/O Base Address
Memory Base Address
Subsystem Vendor ID
Subsystem ID
Cap_Ptr
Interrupt Line
Interrupt Pin
Cap_ID
Next Item Ptr
March 2003 (rev. A)
HFC-4S
HFC-8S
Address
0x2C
0x3C
0x0E
0x2E
0x3D
0x08
0x0F
0x10
0x14
0x40
0x41
0x06
0x09
0x34
Universal external bus interface
3 Bytes
DWord
DWord
Width
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Table 2.8: PCI configuration registers
Default Value
Data Sheet
0x020400
0x1397
0x08B4
0x16B8
0x0210
0xFF
0x00
0x01
0x01
0x00
0x40
0x01
0x00
Remarks
Bits 0 . . . 7 can be set by EEPROM. Base
HFC-4S / 8S Revision 01
Header type 0
Bits 3 . . . 31 are r/w by configuration ac-
Bits 12 . . . 31 are r/w by configuration ac-
Value can be set by EEPROM. Base address
ID of HFC-4S
This register must be configured by config-
INTA# supported
Capability ID. 0x01 identifies the linked list
There are no next items in the linked list.
address for configuration write is 0xC4.
Bits
3..0
4
5
6
7
8
10..9
11
13..12
14
15
Class code for ‘ISDN controller’.Value can
be set by EEPROM. Base address for con-
figuration write is 0xC8.
No build in self test supported.
cesses. 8 Byte address space is used.
cesses. 4 kByte address space is used.
for configuration write is 0xEC.
ID of HFC-8S
Value can be set by EEPROM. Base address
for configuration write is 0xEC.
Offset to Power Management register block.
uration write.
item as PCI Power Management registers.
reserved
’1’ = Capabilities List exists, fixed to ’1’
’0’ = 33 MHz capable (default)
’1’ = 66 MHz capable
reserved
’0’ = fast Back-to-Back not capable (de-
fault)
’1’ = fast Back-to-Back capable
fixed to ’0’
medium
Function
fixed to ’01’: timing of DEVSEL# is
fixed to ’0’
fixed to ’00’
system error (address parity error)
any detected data or system parity error
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Cologne
Chip
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