HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 10

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
10 of 273
2.24 SPI connection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 FSM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.11 General structure of the subchannel processor . . . . . . . . . . . . . . . . . . . . . 113
4.1
4.2
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10 Transformer and connector circuitry in TE mode . . . . . . . . . . . . . . . . . . . 158
5.11 Transformer and connector circuitry in NT mode . . . . . . . . . . . . . . . . . . . 158
6.1
6.2
6.3
8.1
11.1 Points of contact of the various bridge modes . . . . . . . . . . . . . . . . . . . . . 217
11.2 Host bridge structure in I/O mapped mode . . . . . . . . . . . . . . . . . . . . . . . 218
11.3 Host bridge structure in memory mapped mode . . . . . . . . . . . . . . . . . . . . 220
12.1 Standard HFC-4S / 8S quartz circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 230
B.1 Frame structure at reference point S and T . . . . . . . . . . . . . . . . . . . . . . . 268
C.1 HFC-4S / 8S package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Data flow block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Areas of FIFO oriented, HFC-channel oriented and PCM time slot oriented numbering 95
The flow controller in transmit operation
The flow controller in receive FIFO operation . . . . . . . . . . . . . . . . . . . . .
SM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Channel assigner in CSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
CSM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
FIFO / channel assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
FSM list processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
FIFO organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FIFO data organization in HDLC mode . . . . . . . . . . . . . . . . . . . . . . . . 132
S/T clock synchronization shown with one S/T interface in NT mode . . . . . . . . . 148
S/T clock synchronization shown with one S/T interface in TE mode . . . . . . . . . 149
Synchronization scenario with TEs connected to unsynchr. central office switches . . 150
Synchronization registers (detail of Figure 5.3) . . . . . . . . . . . . . . . . . . . . 151
Timing example of one transmit and one receive transmission . . . . . . . . . . . . . 151
External S/T receive circuitry for TE and NT mode . . . . . . . . . . . . . . . . . . 155
External S/T transmit circuitry for TE and NT mode . . . . . . . . . . . . . . . . . . 156
External S/T transmit circuitry for NT mode only . . . . . . . . . . . . . . . . . . . 156
VDD_ST voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
PCM interface function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 175
Example for two CODEC enable signal shapes with SHAPE0 and SHAPE1. . . . . 176
Example for two CODEC enable signal shapes . . . . . . . . . . . . . . . . . . . . 178
Conference example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Data Sheet
. . . . . . . . . . . . . . . . . . . . . . .
March 2003 (rev. A)
Cologne
Chip
85
94
97
98