HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 71

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

16 bit processors can either write data with byte or word access like shown in Figure2.12. FIFO write
access have 8 bit or 16 bit width alternatively. The 16 bit processor must support byte access because
all other register write accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 control the low byte and high byte of the data
bus D15 . . . D0 (see Table 2.19).
Data is written with of (/DS
non-multiplexed). The HFC-4S / 8S requires a data setup time
Address and /BE require a setup time
valid. The hold time of these lines is
March 2003 (rev. A)
HFC-4S
HFC-8S
/WR+/CS
/DS+/CS
/BE[3:2]
D[15:8]
A[7:0]
D[7:0]
Figure 2.12: Byte and word write access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
/BE1
/BE0
R/W
/RD
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
t
RWS
t
t
DWRS
DWRS
t
t
word write access
WR
WR
t
·
data
data
AS
byte enable
byte enable
address
/CS) in mode 2 (Motorola) respective (/WR
Universal external bus interface
t
t
DWRH
DWRH
t
Ø
RWH
t
AH
Ø
À
t
Ë
IDLE
.
which starts when all address and byte enable signals are
Data Sheet
permanently high
permanently high
t
RWS
t
DWRS
t
t
low byte write access
WR
WR
t
data
AS
byte enable
byte enable
address
t
DWRH
t
Ø
RWH
t
AH
Ï Ë
t
IDLE
and a data hold time
t
·
RWS
high byte access
/CS) in mode 3 (Intel,
t
DWRS
t
t
WR
WR
t
data
AS
byte enable
byte enable
address
t
Cologne
Chip
DWRH
t
RWH
t
AH
71 of 273
Ø
Ï À
.