HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 131

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

4.3 FIFO operation
4.3.1 HDLC transmit FIFOs
Data can be transmitted from the host bus interface to the FIFO with write access to the registers
A_FIFO_DATA0 and A_FIFO_DATA0_NOINC. The HFC-4S / 8S converts the data into HDLC
code and tranfers it from the FIFO to the S/T or the PCM bus interface.
The HFC-4S / 8S checks
flag (’01111110’) or continuous ’1’s (depending on the bit V_IFF of the register A_CON_HDLC)
and transmits it to the S/T interface. In this case
HDLC flags or continuous ’1’s are sent to the S/T interface and all counters remain unchanged. If the
frame counters are unequal
to the S/T interface. At the end of a frame (
checksum and adds an ending flag. If there is another frame in the FIFO (
is incremented again.
With every byte being written from the host bus side to the FIFO,
If a complete frame has been sent into the FIFO
If the frame counter
functions of
March 2003 (rev. A)
HFC-4S
HFC-8S
F2
F1
½´ ½µ
is used for the frame which is just written from the host bus side.
G
Without F0IO and C4IO clocks the HDLC controller does not work!
00h
02h
07h
1Fh
½
Important !
and
¾
Z1
Z1
Z1
Z1
Z1
Z1
½
. Thus there are
00
02
is incremented the
06
07
½
and
¾
FIFO handling and HDLC controller
Z1
Z1
is incremented and the HFC-4S / 8S tries to transmit the next frame
00
00
¾
Figure 4.1: FIFO organization
. If
Z2
Z2
00
02
½
½´ ½µ
Data Sheet
¾
reaches
-counters may also change because
¾
,
(FIFO empty) the HFC-4S / 8S generates a HDLC
½
end of frame
end of frame
¾´ ½µ
must be incremented to transmit the next frame.
¾
is not incremented. If also
½
,
) it automatically generates the 16 bit CRC
½´ ¾µ
and
SRAM
½
is incremented automatically.
¾´ ¾µ
½
¾´ ¾µ
frame 02
frame 03
frame 06
frame 07
(see Fig. 4.1).
¾
) the
is used for the
½
½
Cologne
Chip
and
131 of 273
OUTPUT
INPUT
¾
counter
¾
¾
only
are