HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 176

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
HFC-4S
HFC-8S
6.2 PCM initialization
After hard or soft reset the PCM interface starts an initialization sequence to set all A_SL_CFG
registers of the PCM time slots to the reset value 0. This can be done only if valid C4IO and F0IO
signals exist. The initialization process stops after 2 F0IO periods. To check if the initialization
sequence is finished after a reset, the register R_F0_CNTL value must be equal or greater than 2.
6.3 External CODECs
External CODECs can be connected to the HFC-4S / 8S PCM interface. There are two ways of
programming the PCM–CODEC–interconnection. First, a set of eight CODEC enable lines allow to
connect up to eight external CODECs to the HFC-4S / 8S. The second way uses the current time slot
number that must be decoded to a CODEC’s select signal. Then up to 128 external CODECs can be
connected to the HFC-4S / 8S. The choice of these connectivities is done with V_CODEC_CON
of the register R_PCM_MD1.
6.3.1 CODEC select via enable lines
The HFC-4S / 8S has eight CODEC enable signals F1_7 . . . F1_0. Every external CODEC has
to be assigned to a PCM time slot via the bitmaps V_SL_SEL7 . . . V_SL_SEL0 of the registers
R_SL_SEL7 . . . R_SL_SEL0.
Two shape signals can be programmed. The last bit determines the inactive level by which non-
inverted and inverted shape signals can be programmed. Every external CODEC can choose one of the
two shape signals with the bits V_SH_SEL7 . . . V_SH_SEL0 of the registers R_SL_SEL7 . . . R_SL_SEL0.
Figure 6.2 shows an example with two external CODECs with F1_0 and F1_1 enable signals. Time
176 of 273
F0IO
C4IO
F1_0
F1_1
C2O
bit
slot
LSB
0
0 0 1 1 1
Figure 6.2: Example for two CODEC enable signal shapes with SHAPE0 and SHAPE1.
1
low byte
0
1
1 1 1 0 0 0
7
high byte
0 0 0
6
MSB
5
PCM interface
16 C4IO pulses per slot
8 C2O pulses per slot
Data Sheet
4
0
3
2
LSB
1
1 1 1 1 0
1
low byte
0
0
March 2003 (rev. A)
0 0 0 0 0 1
7
high byte
1
Cologne
Chip
1 1 1
6
MSB

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