HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 70

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
must be fulfilled to drive data out. The data bus is stable after
Ø
Address and /BE require a setup time
valid. The hold time of these lines is
Symbol
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Ø
70 of 273
ÊÏË
ÊÏÀ
Ê
Ë
À
Ê
Ê À
Ä
À
.
½ ¡ Ø
min / ns
¡ Ø
¡ Ø
¡ Ø
¡ Ø
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
10
10
20
20
2
2
2
2
Table 2.20: Symbols of read accesses in Figures 2.9 and 2.11
max / ns
15
A[0]
Table 2.19: Data access width in mode 2 and 3
’X’
’0’
’1’
’0’
( : See ‘Short read method’ on page 67.)
Universal external bus interface
/DS+/CS (/RD+/CS)
Characteristic
Address and /BE valid to /DS+/CS (/RD+/CS)
Address hold time after /DS+/CS (/RD+/CS)
/DS+/CS (/RD+/CS)
R/W setup time to /DS+/CS
R/W hold time after /DS+/CS
Read time:
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
Cycle time between two consecutive /DS+/CS (/RD+/CS)
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
/BE1
’1’
’1’
’0’
’0’
– after byte access
– after word access
Ø
Ø
À
Ë
.
/BE0
which starts when all address and byte enable signals are
’1’
’0’
’1’
’0’
Data Sheet
Data access
no access
byte access on D[7:0]
byte access on D[15:8]
word access
to data buffer turn on time
to data buffer turn off time
Ø
Ñ Ò
and returns into tristate after
March 2003 (rev. A)
setup time
Cologne
Chip