HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 105

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

the channel assigner connects the nominated FIFO to HFC-channel
A direct connection between a PCM time slot and an S/T-channel allocates one FIFO although this
FIFO does not store any data. In Channel Select Mode – in contrast to Simple Mode – an arbitrary
FIFO can be chosen. This FIFO must be enabled to switch on the data transmission. If there are less
than 31 FIFOs in transmit and receive direction, it is necessary to select an existing FIFO number.
Subchannel Processing
If more than one FIFO is to be connected to one HFC-channel, this HFC-channel number must be
written into the V_CH_NUM0 bitmap of all these FIFOs. In this case every FIFO contributes one or
more bits to construct one HFC-channel byte. Unused bits of a HFC-channel byte can be set with an
arbitrary mask byte.
In transparent mode the FIFO data rate always remains 8 kByte/s. In HDLC mode the FIFO data rate
is determined by the number of bits transmitted to the HFC-channel.
Please see Section 3.5 on page 113 for details concerning the subchannel processor.
Example for CSM
The example of a Channel Select Mode configuration in Figure 3.7 shows four bidirectional connec-
tions (FIFO-to-S/T, FIFO-to-PCM, PCM-to-S/T and multiple FIFOs to S/T). The black lines illustrate
data paths, whereas the dotted lines symbolize blocked resources. These are not used for data trans-
mission, but they are necessary to enable the settings.
The following settings demonstrate only the required register values to establish the connections.
All involved FIFOs have to be enabled with V_HDLC_TRP
A_CON_HDLC[FIFO]. The non-specified bitmap values depend on the desired FIFO configuration.
March 2003 (rev. A)
HFC-4S
HFC-8S
➊
➋
FIFO-to-S/T
HFC-channel and FIFO numbers can be chosen independently from each other. This is shown
with the FIFO-to-S/T connection:
FIFO-to-PCM
The FIFO-to-PCM connection blocks two S/T-channels and it requires two slot configuration
settings:
A_CHANNEL : V_CH_DIR0[FIFO]
R_FIFO
A_CON_HDLC[4,TX] : V_DATA_FLOW
A_CHANNEL[4,TX] : V_CH_DIR0
R_FIFO
A_CON_HDLC[4,RX] : V_DATA_FLOW
A_CHANNEL[4,RX] : V_CH_DIR0
: V_CH_NUM0[FIFO]
: V_FIFO_DIR
: V_FIFO_NUM
: V_CH_NUM0
: V_FIFO_DIR
: V_FIFO_NUM
: V_CH_NUM0
Data Sheet
Data flow
V_FIFO_DIR
Ò
0
4
’100’
0
0
1
4
’100’
1
0
·
V_TRP_IRQ
Ò
(FIFO
(transmit FIFO)
(FIFO #4)
(transmit HFC-channel)
(HFC-channel #0)
(FIFO
(receive FIFO)
(FIFO #4)
(receive HFC-channel)
(HFC-channel #0)
.
S/T)
S/T)
¼
in the register
Cologne
Chip
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