HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 135

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
4.3.7 Reading - and -counters
For all asynchronous host accesses to the HFC-4S / 8S there is a small chance that a register is
changed just in the moment when it is read. Because of slightly different delays of individual bits, it
is even possible that the read value is fully invalid. Therefore we advise to read a
register until two consecutive readings find the same value.
This is not necessary for a time period of at least 125 s after writing R_FIFO. It is also not necessary
for -counters of receive FIFOs if
March 2003 (rev. A)
HFC-4S
HFC-8S
½´ ¾µ
and
¾´ ¾µ
are stable and valid.
FIFO handling and HDLC controller
½
¾
. Then a whole frame has been received and the counters
Data Sheet
- or
Cologne
Chip
135 of 273
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