HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 108

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
3.4.3 FIFO Sequence Mode
In contrast to the PCM and S/T-channels, the FIFO data rate is not fixed to 8 kByte/s. In the previous
section the CSM allows the functional capability of a FIFO data rate less than 8 kByte/s. In this
section, the third data flow mode shows how to use FIFOs with a higher data rate with the FIFO
Sequence Mode (FSM). In transmit direction one FIFO can cyclically distribute its data to several
HFC-channels. In opposite direction, received data from several HFC-channels can be collected
cyclically in one FIFO (see Fig. 3.8, right side). A one-to-one connection between FIFO and HFC-
channel is of course possible in FSM, too (Fig. 3.8, left side).
FIFO Sequence Mode is selected with V_FSM_MD = ’1’ in the register R_FIFO_MD). CSM and
FSM should be used at the same time. Actually, this is necessary for nearly all FSM applications.
The HFC-4S / 8S works in Simple Mode if none of these two modes is selected.
FIFO sequence
To achieve a FIFO data rate higher than 8 kByte/s a FIFO must be connected to more than one HFC-
channel. As there is only one register A_CHANNEL[FIFO] the FSM programming path must differ
from the previous modes.
In FSM all FIFOs are organized in a list with up to 64 entries. Every list entry is assigned to a FIFO.
FIFO configuration can be set up as usual. I.e. HFC-channel allocation, flow controller programming
and subchannel processing can be configured as described in the previous sections. Additionally, each
list entry specifies the next FIFO of the sequence. The list is terminated by an ‘end of list’ entry. This
procedure is shown in Figure 3.9 with
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In addition to the above register settings, the subchannel processor must be configured now. It is
important to see that the subchannel processor programming has no influence to the connection
setup. So there is no need to describe these settings here. Please see Section3.5 on page 113
for a detailed subchannel description.
G
In Channel Select Mode
Rule
every HFC-channel used requires at least one enabled FIFO (except for the
PCM-to-PCM connection) with the same data direction and
every PCM time slot used requires one HFC-channel (except for the PCM-
to-PCM connection where a full duplex connection allocates one HFC-
channel).
FIFO
assigner
assigner
channel
channel
Figure 3.8: FIFO / channel assigner
Channel
· ½
Data Sheet
list entries.
Data flow
FIFO
assigner
assigner
channel
channel
Channels
Channels
March 2003 (rev. A)
Cologne
Chip