HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 268

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
The frame structures on the S/T interface are different for each direction of transmission. Both struc-
tures are illustrated in Figure B.1.
Legend:
268 of 273
Code
F
L
D
E
F
M
0
1
0
D
G
Lines demarcate those parts of the frame that are independently DC balanced.
The F bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q
bit transmission is enabled (see A_ST_CTRL0 register).
The nominal 2 bit offset is as seen from the TE. The offset can be adjusted with
the A_ST_CLK_DLY register in TE mode. The corresponding offset at the NT
may be greater due to delay in the interface cable and varies by configuration.
HDLC B-channel data start with the LSB, PCM B-channel data start with the
MSB.
L .
t
F
D
2 bits offset
L
L .
NOTE !
.
B1
F
Explanation
Framing bit
DC balancing bit
D-channel bit
D-echo-channel bit
Auxiliary framing bit
Multiframing bit
B1
L
NT to TE
TE to NT
.
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
Figure B.1: Frame structure at reference point S and T
B1
E
B1
D
A
L .
F
D
A
N
L
.
B2
F
A
B2
L
.
B2
B2
B2
B2
48 bits in 250 microseconds
B2
B2
B2
B2
B2
B2
B2
B2
B1
B2
A
S
Code
N
Data Sheet
B2
E
B2
D
M
L .
B1
D
B1
L
.
Explanation
Bit within B-channel 1
Bit within B-channel 2
Bit used for activation
S-channel bit
Bit set to a binary value Æ
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
E
B1
D
S
L .
B2
D
B2
L
.
B2
B2
DC balanced parts
B2
B2
of different TEs
B2
B2
(see note)
B2
B2
B2
B2
B2
B2
B2
E
B2
D
March 2003 (rev. A)
L .
L .
F
D
L
L
(NT to TE)
.
.
F
L
.
Cologne
Chip