HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 68

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
8 bit processors write data like shown in Figure 2.10. Timing values are listed in Table 2.21.
/BE3 . . . /BE1 must always be ’1’. /BE0 controls the data bus D7 . . . D0 and can be fixed to ’0’.
Data is written with of (/DS
non-multiplexed). The HFC-4S / 8S requires a data setup time
Address and /BE0 (if not fixed to low) require a setup time
byte enable signals are valid. The hold time of these lines is
68 of 273
/WR+/CS
/DS+/CS
/BE[3:1]
D[15:8]
A[7:0]
D[7:0]
/BE0
R/W
/RD
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
Figure 2.10: Write access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
t
RWS
t
DWRS
t
t
byte write access
WR
WR
t
·
data
AS
address
/CS) in mode 2 (Motorola) respective (/WR
Universal external bus interface
t
DWRH
t
RWH
t
AH
Data Sheet
permanently high
permanently high
permanently low
t
IDLE
Ø
Ø
À
Ø
Ë
.
Ï Ë
which starts when all address and
t
RWS
and a data hold time
t
DWRS
t
t
byte write access
WR
WR
t
data
AS
·
address
March 2003 (rev. A)
/CS) in mode 3 (Intel,
t
DWRH
t
RWH
t
AH
Cologne
Chip
Ø
Ï À
.