HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 166

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
166 of 273
A_ST_CLK_DLY [ST]
Clock control register of the S/T module
This register is not initialized after reset. It must be initialized before activating the TE / NT
state machine.
Before writing this array register the S/T interface must be selected by register R_ST_SEL.
3..0
6..4
7
Bits
Value
Reset
Name
V_ST_CLK_DLY
V_ST_SMPL
(reserved)
S/T interface
(write only)
Data Sheet
Description
S/T clock delay
TE mode: 4 bit delay value to adjust the 2 bit time
between receive and transmit direction. The delay
of the external S/T interface circuit can be
compensated. The lower the value the smaller the
delay between receive and transmit direction. The
suitable value is 0xE for normal external
circuitries.
NT mode: Data sample point. The lower the value
the earlier the input data is sampled. The normal
operation value is 0xC.
For both modes the steps are 163 ns.
Early edge input data shaping
(NT mode only)
Low pass characteristic of extended bus
configurations can be compensated. The lower the
value the earlier input data pulse is sampled. The
default value is 6 (’110’ ) which means that no
compensation is carried out. Step size is 163 ns.
Must be ’0’.
March 2003 (rev. A)
Cologne
Chip
0x37