HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 210

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
10.1 BERT functionality
Bit Error Rate Test (BERT) is a very important test for communication lines. The bit error rate should
be as low as possible. Increasing bit error rate is an early indication of a malfunction of components
or the communication wire link itself.
HFC-4S / 8S includes a high performance pseudo random bit generator (PRBG) and a pseudo ran-
dom bit receiver with automatic synchronization capability. Error rate can be checked by the also
implemented Bit Error counter (BERT counter).
The PRBG can be set to a variety of different pseudo random bit patterns. With the bit pattern
V_PAT_SEQ in register R_BERT_WD_MD the transmit and receive detector can be set to the
trivial always ’0’ or always ’1’ pattern as well to well known patterns described in ITU-T O.150 and
O.151 specifications.
In every transmit HFC-channel the HDLC or transparent data is overwritten by bits from the PRBG
if V_BERT_EN in the register A_IRQ_MSK[FIFO] is set to ’1’. The random data is only gener-
ated when the FIFO is processing data. So if subchannel processing is enabled the PRBG is only
enabled for less than 8 bits. Next PRGB bits are generated in the next FIFO where a HFC-channel is
processed and V_BERT_EN is set. The receive detector can function properly only when the same
receive FIFOs connected to the same S/T-channels are enabled for BERT in receive direction as on
the transmit FIFOs of the remote S/T interface side.
The receive detector has an auto synchonization capability and also is enabled to automatic detect
an inverted BERT pattern. The auto synchronization only works with bit error rates of less than
reported by V_BERT_SYNC
V_BERT_INV_DATA is set.
A 16 bit BERT error count is available by reading the registers R_BERT_ECL and R_BERT_ECH.
The counter is reset when the R_BERT_ECL register is read.
To test a connection and the error detection of the BERT error counter on the receiver side of an S/T
link a BERT error can be generated. Setting the V_BERT_ERR generates one wrong BERT bit in
the outgoing data stream.
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¡
½¼
¾
. If the error rate is higher synchronization will not be achieved. A found synchronization is
½
in register R_BERT_STA. If the received pattern is inverted also
Data Sheet
BERT
March 2003 (rev. A)
Cologne
Chip