HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 133

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

Remember that an increment of -value
There are two different FIFO full conditions. The first one is met when the FIFO contents comes up
to 31 frames (128k or 512k RAM) or 15 frames (32k RAM). There is no possibility for HFC-4S / 8S
to manage more frames even if the frames are very small. The second limitation is the overall size of
the FIFO.
4.3.4 HDLC receive FIFOs
The receive HFC-channels receive data from the S/T or PCM bus interface read registers. The data
is converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host
bus interface.
The HFC-4S / 8S checks the HDLC data coming in. If it finds a flag or more than 5 consecutive
’1’s it does not generate any output data. In this case
being received is converted by the HFC-4S / 8S into plain data. After the ending flag of a frame
the HFC-4S / 8S checks the HDLC CRC checksum. If it is correct one byte with all ’0’s is inserted
behind the CRC data in the FIFO named STAT (see Fig. 4.2). This last byte of a frame in the FIFO is
different from all ’0’s if there is no correct CRC field at the end of the frame.
If the STAT value is 0xFF, the HDLC frame ended with at least 8 bits ’1’s. This is similar to an abort
HDLC frame condition.
The ending flag of a HDLC frame can also be the starting flag of the next frame.
After a frame is received completely
next frame can be received.
After reading a frame via the host bus interface
incremented also the -counters may change because
there are
the end of frame pointer of the current output frame.
To calculate the length of the current receive frame the software has to evaluate
In the receive HFC-channels
detects an end of receive frame (
V_INC_F in the register R_INC_RES_FIFO. If
March 2003 (rev. A)
HFC-4S
HFC-8S
½´ ½µ
¾´ ¾µ
¾
½´ ½µ
¾
reaches
is incremented and
is used for the frame which is just received from the S/T interface side of the HFC-4S / 8S.
can not be accessed.
is used for the frame which is just beeing transmitted to the host bus interface.
G
Before reading a new frame, a change FIFO operation (write access to the register
R_FIFO) has to be done even if the desired FIFO is already selected. The change
FIFO operation is required to update the internal buffer of the HFC-4S / 8S. Oth-
erwise the first 4 bytes of the FIFO will be taken from the internal buffer and may
be invalid.
½´ ½µ
½
Important !
the complete frame has been read.
,
¾´ ½µ
¾
,
is copied as start address of the next frame. This is done by setting the bit
½´ ¾µ
FIFO handling and HDLC controller
¾
must be incremented from the host interface side after the software
½
and
½
is incremented by the HFC-4S / 8S automatically and the
¾
Å
¾´ ¾µ
) and
Data Sheet
is
¾
(see Fig. 4.1).
½
has to be incremented. If the frame counter
½
ÅÁÆ
½
in all FIFOs!
½
¾
¾
and
. Then the current value of
and
is not incremented. Proper HDLC data
¾
½
are functions of
¾
the FIFO is totally empty.
½
½
and
¾ · ½
Cologne
Chip
¾
133 of 273
is stored,
½´ ¾µ
¾
. When
. Thus
¾
is
is