HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 147

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

5.1 State machine
A specification conform state machine for TE and NT mode is implemented. So the Fx or Gx state
can be read out of the register A_ST_RD_STA. However, it is possible to overwrite the state machine
by setting the bit V_ST_LD_STA of the register A_ST_WR_STA. Activation and deactivation can
be initiated by writing the bitmap V_ST_ACT in the same register.
Before starting the Fx / Gx state machine, the register A_ST_CLK_DLY of its S/T interface must be
set. For TE the default value is 0x0F and for NT the default value is 0x6C.
There is an overview register R_SCI which reports a state change of all S/T interfaces. Bits which
are masked as enabled in the register R_SCI_MSK also generate an interrupt. All bits in R_SCI are
cleared after reading the register.
March 2003 (rev. A)
HFC-4S
HFC-8S
G
The S/T state machine is stuck to ’0’ after a reset. In this state the HFC-4S / 8S
sends no signal on the S/T line and is not able to activate it by incoming INFOx.
Writing a ’0’ to bit V_ST_LD_STA of the A_ST_WR_STA register restarts the
state machine.
NT mode: The NT state machine does not change automatically from G2 to G3
if the TE side sends INFO3 frames. This transition must be activated each time
by V_G2_G3 of the A_ST_RD_STA register or by setting bit V_G2_G3_EN
of the A_ST_CTRL1 register.
Important !
S/T interface
Data Sheet
Cologne
Chip
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