HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 109

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

A quite simple FSM configuration with every FIFO and every HFC-channel specified only one time
in the list, would have the same data transmission result as the CSM with an equivalent FIFO
HFC-channel setup. But if a specific FIFO is selected
HFC-channels, the FIFO data rate is
The complete list is processed every 125 s with ascending list index beginning with 0. Suppose the
transmit FIFO
connected HFC-channel, the second byte of FIFO
on. This is similar to the receive data direction. The first byte written into FIFO
first connected HFC-channel, the second byte from the second connected HFC-channel and so on.
March 2003 (rev. A)
HFC-4S
HFC-8S
R_FSM_IDX
G
FIFO data rates higher than 8 kByte/s require an arbitrary assignment between
a FIFO number and the connected HFC-channel. Therefore, the Channel Select
Mode must be enabled. For this reason FSM is mostly selected in combination
with CSM. All data transfer configuration possible with FSM but without CSM
are also possible with CSM only – but with lower configuration effort!
Important !
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occurs several times in the list. Then the first FIFO byte is transferred to the first
Index
R_FIFO_START
List
63
...
...
...
0
1
2
i
j
1st FIFO
FIFO m
FIFO n
FIFO q
FIFO
Figure 3.9: FSM list processing
...
Ò
¡
Data Sheet
Channel
ÝØ ×
Data flow
channel a
channel b
channel d
channel e
channel c
.
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List Entries:
Ò
to the second connected HFC-channel and so
configuration
configuration
configuration
configuration
configuration
Register
settings
times in the list and connected to
...
...
end of list
1st FIFO
FIFO m
FIFO n
FIFO o
FIFO q
FIFO
Next
A_CON_HDLC [i]
A_BYTE_PAR [i]
A_FIFO_SEQ [i]
A_CHANNEL [i]
Ñ
A_IRQ_MSK [i]
comes from the
Cologne
Chip
109 of 273
Ò
different