HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 74

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
8 bit processors write data like shown in Figure 2.14. Timing values are listed in Table 2.24.
/BE3 . . . /BE1 must always be ’1’. /BE0 controls the data bus D7 . . . D0 and can be fixed to ’0’.
Data is written with
data setup time
Address and /BE0 (if not fixed to low) require a setup time
hold time of these lines is
register address write is not required.
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/WR+/CS
AD[31:8]
/BE[3:1]
A[7:0]
/BE0
ALE
/RD
Figure 2.14: Write access from 8 bit processors in mode 4 (Intel, multiplexed)
Ø
t
address
ALE
Ï Ë
t
AS
address
of (/WR
and a data hold time
t
AH
Ø
À
t
. If two consecutive write accesses are on the same address, multiple
ALEH
·
Universal external bus interface
/CS) in mode 4 (Intel, multiplexed). The HFC-4S / 8S requires a
byte write access
Data Sheet
Ø
t
t
DWRS
WR
Ï À
permanently high
permanently high
permanently low
data
.
t
DWRH
Ø
t
Ë
IDLE
which starts with the
byte write access
t
t
WR
DWRS
March 2003 (rev. A)
data
of ALE. The
Cologne
Chip
t
DWRH