HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 238

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
238 of 273
R_IRQ_FIFO_BL0
FIFO interrupt register for FIFO block 0
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is
’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
Name
V_IRQ_FIFO0_TX
V_IRQ_FIFO0_RX
V_IRQ_FIFO1_TX
V_IRQ_FIFO1_RX
V_IRQ_FIFO2_TX
V_IRQ_FIFO2_RX
V_IRQ_FIFO3_TX
V_IRQ_FIFO3_RX
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Interrupt occured in transmit FIFO 0
Interrupt occured in receive FIFO 0
Interrupt occured in transmit FIFO 1
Interrupt occured in receive FIFO 1
Interrupt occured in transmit FIFO 2
Interrupt occured in receive FIFO 2
Interrupt occured in transmit FIFO 3
Interrupt occured in receive FIFO 3
March 2003 (rev. A)
Cologne
Chip
0xC8