HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 55

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

2.3.1 IRQ assignment
The IRQ lines are tristated after a hardware reset.
The IRQ assigned by the PnP BIOS can be read from the bitmap V_PNP_IRQ of the register
R_CHIP_ID. The bitmap V_IRQ_SEL of the register R_CIRM has to be set according to the IRQ
wiring between HFC-4S / 8S and the ISA slot on the PCB. Thus the IRQ number assigned by the
PnP BIOS is connected to the right IRQ line on the ISA bus.
2.3.2 ISA Plug and Play registers
control register
March 2003 (rev. A)
HFC-4S
HFC-8S
/BUSDIR
/BUSDIR
Card level
address
0x00
0x01
0x02
¼
½
means that the HFC-4S / 8S is read and data is driven to the external bus.
means that data is driven (written) into the HFC-4S / 8S.
Read / write
Mode
w
w
r
Isolation state,
Config state
Isolation state,
Isolation state
Config state
Accessable
Sleep state,
Universal external bus interface
Table 2.11: ISA Plug and Play registers
in state
Data Sheet
Description
Set read data port address register.
Bits 0 . . . 7 become bits 2 . . . 9 of the port’s I/O address.
Bits 10 and 11 are hardwired to ’00’ and bits 0 and 1 are
hardwired to ’11’.
Serial isolation register.
Used to read the serial identifier during the card isolation
process.
Configuration control register.
Bits
0
1
2
7..3
Function
Reset Bit. The value ’1’ resets all of the card’s configuration
registers to their default state. The CSN is not affected.
Return to wait for key state. When set to one, all cards
return to wait for key state. Their CSNs and configuration
registers are not affected. This command is issued after all
cards have been configured and activated.
Reset CSN to zero. When set to one, all cards reset their
CSN to zero. All bits are automatically cleared by the hard-
ware.
Reserved, must be zero
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Cologne
Chip
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