HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 78

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
must be fulfilled to drive data out. The data bus is stable after
Ø
Address and /BE require a setup time
lines is
is not required.
An 8 bit read access (low byte) is performed in the same way as it is done with 8 bit processors. Thus
see Figure 2.13 for the timing specification.
Symbol
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Ø
78 of 273
Ê
Ä
Ä À
Ë
À
Ê
Ê À
Ä
À
.
Ø
À
½ ¡ Ø
. If two consecutive read accesses are on the same address, multiple register address write
min / ns
¡ Ø
¡ Ø
¡ Ø
¡ Ø
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
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Table 2.23: Symbols of read accesses in Figures 2.13, 2.15 and 2.17
10
10
10
20
20
20
0
2
2
max / ns
15
( : See ‘Short read method’ on page 67.)
Universal external bus interface
/RD+/CS
Characteristic
Address latch time
ALE
Address and /BE valid to /RD+/CS
Address hold time after /RD+/CS
/RD+/CS
Read time:
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
Cycle time between two consecutive /RD+/CS
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
– after byte access
– after word access
Ø
Ë
to /WR+/CS
which starts with the
Data Sheet
to data buffer turn on time
to data buffer turn off time
Ø
Ñ Ò
of ALE. The hold time of these
setup time
and returns into tristate after
March 2003 (rev. A)
Cologne
Chip