HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 271

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

List of register and bitmap abbreviations
This list shows all abbreviations which are used to define the register and bitmap names. Appended
digits are not shown here except they have a particular meaning.
96KHZ
ACT
ADDR
ADDR0
ADDR1
ADDR2
ADJ
ATT
AUTO
B1
B12
B2
BERT
BIT
BL
BRG
BUSY
C4
CFG
CH
CHANNEL HFC-channel
CHIP
CLK
CNT
CNTH
CNTL
CON
CONF
CS
CSM
March 2003 (rev. A)
96 kHz
activate
address
address (byte 0)
address (byte 1)
address (byte 2)
adjust
attenuation
automatic
B1-channel
B1- and B2-channel
B2-channel
bit error rate test
bit
block
bridge
busy
C4IO clock
configuration
HFC-channel
chip
clock
counter
counter, high byte
counter, low byte
connection settings
conference
chip select
channel select
mode
CTRL
D
DATA
DEC
DIR
DLY
DR
DTMF
E
ECH
ECL
EN
END
EOMF
EPR
ERR
EV
EXP
EXT
F
F0
F1
F12
F2
FIFO
FIRST
FLOW
Data Sheet
control
D-channel
data
decoder
direction
delay
data rate
dual tone multiple
frequency
E-channel
error counter, high
byte
error counter, low
byte
enable
end
end of multiframe
EEPROM
error
event
external
F-counter
frame
syncronization
signal
F1-counter
F1- and F2-counter
F2-counter
FIFO
first
flow
expire
FR
FSM
G2
G3
GLOB
GPI
GPIO
HARM
HDLC
HFCRES
HI
ICR
ID
IDLE
IDX
IFF
IGNO
IN
INC
INFO0
INT
INV
IRQ
IRQ1S
IRQMSK
IRQSTA
frame
FIFO sequence
mode
G2 state
G3 state
global
general purpose
input
general purpose
input/output
harmonic
high-level data link
control
HFC reset
high
increase
identifier
idle
index
inter frame fill
ignore
input
increment
INFO 0 line
condition (no
signal)
internal
invert
interrupt
one-second
interrupt
interrupt mask
interrupt status
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