HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 19

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
Chapter 1
General description
March 2003 (rev. A)
(required for
PCMCIA and
ISA-PnP,
optional for PCI)
128K x 8
512K x 8
EEPROM
SRAM
HFC - 8S
Controller
64 FIFOs
32K x 8
RAM
FIFO
for
32 for Receive:
32 for Transmit:
Controllers
HDLC / Transparent
Mode Select
for Channel
HDLC
64
TM
B, D, PCM
B, D, PCM
Universal External Bus Interface
Microprocessor Interface / SPI
FIFO
Figure 1.1: HFC-8S block diagram
Configuration Registers
Channel
Transmit/Receive
Channel
for FIFO
PCI / ISA-PnP / PCMCIA /
Data Sheet
Processing
Channel
Sub-
Bit Count /
Start Bit /
Mask Bits
Connect
Conference /
DTMF and
Connect
Options
Detect
Confe-
rence
DTMF
Channel
Assigner
Timeslot
Select PCM
Timeslot
Slot
Interface
8 S/T Interfaces
Bridge
S/T
PCM128 /
PCM64 /
PCM30
Interface
19 of 273
8x S/T
CODEC
Select
PCM128
PCM64
PCM30
MST
(IOM2)
(GCI)
8 Bit

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