HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 149

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

5.2.2 Clock synchronization in TE mode
The C4IO clock is adjusted in the last time slot of the PCM frame 1 to 4 times by a half clock cycle
at the 16384 kHz clock (see R_PCM_MD1 register). This is useful if another HFC series ISDN
controller is connected as slave in NT mode to the PCM bus. The sync source can be selected by the
R_PCM_MD2 register settings.
In auto select mode (see Figure 5.2) a synchronized TE is selected as synchronization source. If
synchronization is lost on this TE the next one with active synchronization is selected.
March 2003 (rev. A)
HFC-4S
HFC-8S
S/T interface in TE mode
RX
TX
* A synchronization signal is only generated
192 kHz
if the S/T interface is activated (F7 state).
Otherwise the signal is '0'.
PCM data
controller
Figure 5.2: S/T clock synchronization shown with one S/T interface in TE mode
receive
DPLL
delay
clock
192 kHz
8 resp. 4 S/T interfaces
controller
S/T data
frame
sync
8 kHz
6.144 MHz
8 kHz
*
S/T interface
DPLL
PCM
Data Sheet
divider
select
s y n c
select
divider
or 8192 kHz
or 4096 kHz
MUX
select
16384 kHz
÷ 4
MUX
auto-
8 / 4
with
3
auto
select
select
input
1
sync
divider
÷ 1.5
MUX
8 kHz from
interface in
TE mode
divider
divider
÷ 2048
÷ 1024
÷ 512
÷ 2
output
sync
select
24.576 MHz
PCM Master
Cologne
Chip
PCM interface
149 of 273
8 kHz
SYNC_I
SYNC_O
C2O
C4IO
F0IO