IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 98

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–4
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
PHY Interface Logic
ODT Generation Logic
Low-Power Mode Logic
1
When the main state machine issues a write command to the memory, the write data
for that write burst has to be fetched from the write data FIFO buffer. The relationship
between write command and write data depends on the memory type, ALTMEMPHY
interface type, CAS latency, and the full-rate or half-rate setting. The PHY interface
logic adjusts the timing of the write data FIFO read request signal so that the data
arrives on the external memory interface DQ pins at the correct time.
The ODT generation logic (not shown in
long to enable the ODT outputs. It also decides which ODT bit to enable, based on the
number of chip selects in the system.
■
■
Table 6–1. ODT
The low-power mode logic (not shown in
local_powerdn_req and local_self_rfsh_req request signals. This logic also informs
the user of the current low-power state via the local_powerdn_ack and
local_self_rfsh_ack acknowledge signals.
HPC supports only precharge power-down mode and not active power-down mode.
1 DIMM (1 or 2 chip selects)
In the case of a single DIMM, the ODT signal is only asserted during writes. The
ODT signal on the DIMM at mem_cs[0] is always used, even if the write command
on the bus is to mem_cs[1]. In other words, mem_odt[0] is always asserted even if
there are two ODT signals.
2 or more DIMMs
In the multiple DIMM case, the appropriate ODT bit is asserted for both read and
writes.
Table 6–1
mem_cs[2] or cs[3]
mem_cs[4] or cs[5]
mem_cs[6] or cs[7]
mem_cs[0]or cs[1]
Write or Read On
shows which ODT signal on the adjacent DIMM is enabled.
Chapter 6: Functional Description—High-Performance Controller
Figure
Figure
6–2) calculates when and for how
6–2) monitors the
December 2010 Altera Corporation
ODT Enabled
mem_odt[2]
mem_odt[0]
mem_odt[6]
mem_odt[4]
Block Description