IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 97

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Block Description
December 2010 Altera Corporation
Write Data Tracking Logic
Main State Machine
Bank Management Logic
Timer Logic
Initialization State Machine
Address and Command Decode
The write data tracking logic keeps track of the number of write data beats in the FIFO
buffer. In native interface mode, this logic manages how much more data to request
from the user logic and issues the local_wdata_req signal.
The main state machine decides what DDR commands to issue based on inputs from
the command FIFO buffer, the bank management logic, and the timer logic.
The bank management logic keeps track the current state of each bank. It can keep a
row open in every bank in your memory system. The state machine uses the
information provided by this logic to decide whether it needs to issue bank
management commands before it reads or writes to the bank. The controller always
leaves the bank open unless the user requests an auto-precharge read or write. The
periodic refresh process also causes all the banks to be closed.
The timer logic tracks whether the required minimum number of clock cycles has
passed since the last relevant command was issued. For example, the timer logic
records how many cycles have elapsed since the last activate command so that the
state machine knows it is safe to issue a read or write command (t
logic also counts the number of clock cycles since the last periodic refresh command
and sends a high priority alert to the state machine if the number of clock cycles has
expired.
The initialization state machine issues the appropriate sequence of command to
initialize the memory devices. It is specific to DDR3 as each memory type requires a
different sequence of initialization commands.
With the AFI, the ALTMEMPHY megafunction initializes the memory, otherwise the
controller is responsible for initializing the memory.
When the state machine wants to issue a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these into the
DDR-specific RAS, CAS, and WE commands.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
RCD
). The timer
6–3