IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 62

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–10
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1
1
On multiple rank DDR3 SDRAM DIMMs, address signals are routed differently to
each rank (referred to in the JEDEC specification as address mirroring). Ranks with
address mirroring can be specified in the memory Preset Editor in the Mirror
addressing field.
RTL simulation of address mirroring is not currently supported by the memory model
generated with the example testbench. To simulate successfully, you need a DDR3
DIMM model compatible with address mirroring.
Step 2: Write Leveling
This step aligns the DQS edge with the CK edge at each memory device in the DIMM,
which includes calibrating the write-leveling delay chains, programmable output
delay chain, and using the t
relationship between the DQS edge and the CK edge. The calibration uses one DQ pin
per DQS group (prime DQ) for write leveling calibration.
Step 3: Write Training Patterns
This step only allows you to write a pattern to be read later to calibrate the read path.
To satisfy the DDR3 SDRAM JEDEC specification, DQ is held constant during this
step to ensure that there are no DQ timing violations. The DQS is then toggled,
followed by a write command. A combination of burst length of four and burst length
of eight operations ensure that it is correctly written. There are three different DQ
patterns written in this step:
■
■
■
Step 4: Read Resynchronization
This step adjusts the phase of the resynchronization clock to determine the optimal
clock phase that gives the most margin, similar to the resynchronization calibration
done in DDR and DDR2 SDRAM PHYs.
This step uses the read-leveling delay chain and the PLL reconfigurable clock output
to adjust the resynchronization clock phase for each DQS group.
Step 5: Address and Command Path Clock Cycle
This step word-aligns the read data within and between each DQS group so that data
can be presented in one clock cycle.
Step 6: Postamble
This step sets the correct clock cycle and clock phase shift for the postamble path.
With the read resynchronization process, the sequencer can approximate when the
postamble enable must be asserted. The sequencer then tries to incrementally assert
the postamble enable signal (per DQS group) earlier until there is a read failure. This
ensures the optimal clock phase for the system's postamble enable signal.
All 0: 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00
All 1: 0×FF, 0×FF, 0×FF, 0×FF, 0×FF, 0×FF, 0×FF, 0×FF
Mixed: 0×00, 0×00, 0×00, 0×00, 0×FF, 0×FF, 0×FF, 0×FF
DQSS
-margin register in the DDR3 SDRAM to monitor the
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
Block Description