IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 141

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–20. Address 0x126 Memory Timing Parameters Register 3
Table 7–21. Address 0x130 ECC Control Register
Table 7–22. Address 0x131 ECC Status Register (Part 1 of 2)
December 2010 Altera Corporation
15:12
31:16
11:8
Bit
3:0
7:4
Bit
Bit
7:2
0
1
2
3
4
5
6
7
9
0
1
CAS latency, t
Additive latency, AL
CAS write latency,
CWL
Write recovery, t
Reserved
ENABLE_ECC
ENABLE_AUTO_CORR
GEN_SBE
GEN_DBE
ENABLE_INTR
MASK_SBE_INTR
MASK_DBE_INTR
CLEAR
Reserved
SBE_ERROR
DBE_ERROR
Reserved
Name
Name
Name
CL
WR
Default
Default
—
—
—
—
0
0
0
0
Default
—
1
0
0
1
0
0
0
0
Access
Access
RW
RW
RW
RW
RO
RO
—
—
Access
RW
RW
RW
RW
RW
RW
RW
RW
—
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
This value must be set to match the memory CAS
latency. You must set this value in the 0x04
register map as well.
Additive latency setting. The default value for
these bits is set in the Memory additive CAS
latency setting in the Preset Editor dialog box.
You must set this value in the 0x05 register map
as well.
CAS write latency setting. You must set this value
in the 0x06 register map as well.
This value must be set to match the memory
write recovery time (t
value in the 0x04 register map as well.
Reserved for future use.
Set to 1 when any single-bit errors occur.
Set to 1 when any double-bit errors occur.
Reserved for future use.
When 1, enables the generation and checking
of ECC.
When 1, enables auto-correction when a
single-bit error is detected.
When 1, enables the deliberate insertion of
single-bit errors, bit 0, in the data written to
memory. This bit is only used for testing
purposes.
When 1, enables the deliberate insertion of
double-bit errors, bits 0 and 1, in the data
written to memory. This bit is only used for
testing purposes.
When 1, enables the interrupt output.
When 1, masks the single-bit error interrupt.
When 1, masks the double-bit error interrupt
When 1, writing to this self-clearing bit clears
the interrupt signal, and the error status and
error address registers.
Reserved for future use.
External Memory Interface Handbook Volume 3
Description
Description
Description
WR
). You must set this
7–25