IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 126

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–10
Example Top-Level File
Figure 7–5. Testbench and Example Top-Level File
Table 7–2. Example Top-Level File and Testbench Files
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
<variation name>_example_top_tb.v or .vhd
<variation name>_example_top.v or .vhd
<variation name>_mem_model.v or .vhd
<variation name>_full_mem_model.v or .vhd
<variation name>_example_driver.v or .vhd
<variation name> .v or .vhd
<variation name>.qip
test_complete
clock_source
pnf
The MegaWizard Plug-In Manager helps you create an example top-level file that
shows you how to instantiate and connect the DDR3 SDRAM HPC II. The example
top-level file consists of the DDR3 SDRAM HPC II, some driver logic to issue read
and write requests to the controller, a PLL to create the necessary clocks, and a DLL
(Stratix series only). The example top-level file is a working system that you can
compile and use for both static timing checks and board tests.
Figure 7–5
Table 7–2
testbench.
There are two Altera-generated memory models available—associative-array
memory model and full-array memory model.
The associative-array memory model (<variation name>_mem model.v) allocates
reduced set of memory addresses with a default depth of 2,048 or 2K address spaces.
This allocation allows for a larger memory array compilation and simulation which
enables you to easily reconfigure the depth of the associate array.
The full-array memory model (<variation name>_mem model_full.v) allocates
memory for all addresses accessible by the DDR cores. This allocation makes it
impossible to simulate large memory designs.
Filename
Testbench
Example Design
Example Driver
describes the files that are associated with the example top-level file and the
shows the testbench and the example top-level file.
DDR SDRAM Controller
Control
Logic
Testbench for the example top-level file.
Example top-level file.
Associative-array memory model.
Full-array memory model.
Example driver.
Top-level description of the custom MegaCore function.
Contains Quartus II project information for your MegaCore
function variations.
Chapter 7: Functional Description—High-Performance Controller II
ALTMEMPHY
DLL
PLL
Description
December 2010 Altera Corporation
Memory Model
Generated
Wizard-
Example Top-Level File