IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 70

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–18
Figure 5–8. ALTMEMPHY Reset Management Block for Stratix IV and Stratix III Devices
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Another
system
clock
Read Datapath
reset counter, not
created by the PHY
edge detect and
reset_ request_n
Optional
clk_div_reset_ams_n
This topic discusses the read datapath.
Arria II GX Devices
The read datapath logic captures data sent by the memory device and subsequently
aligns the data back to the system clock domain. The read datapath for DDR3 SDRAM
consists of the following three main blocks:
■
■
■
As the DQS/DQSn signal is not continuous, the PHY also has postamble protection
logic to ensure that any glitches on the DQS input signals at the end of the read
postamble time do not cause erroneous data to be captured as a result of postamble
glitches.
Data capture
Data resynchronization
Data demultiplexing and alignment
D
global_reset_n
CLR
SET
soft_reset_n
Q
Q
pll_ref_clk
clk_div_reset_ams_n_r
pll_reconfig_reset_n
D
SET
CLR
Q
Q
clk_divider_reset_n
phy_clk
reset_n
divider
circuit
scan _ clk
clk
pll_reset
(active HIGH)
refclk
global_or_soft_reset_n
areset
PLL
locked
c0
pll_locked
Chapter 5: Functional Description—ALTMEMPHY
pll_reconfig_reset_ams_n
reset_master_ams
phy_internal_reset_n
D
CLR
SET
D
CLR
SET
Q
Q
Q
Q
December 2010 Altera Corporation
D
SET
CLR
D
CLR
pll_reconfig_reset_ams_n_r
global_pre_clear
SET
Q
Q
Q
Q
Internal reset signal
signal for the
PLL clock-domain
crossing registers
Reset
Pipes
Block Description
reset_request_n
phy_clk_out
PHY resets