IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 113

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
Table 6–13. Local Interface Signals (Part 3 of 4)
December 2010 Altera Corporation
local_powerdn_req
local_self_rfsh_req
phy_clk
reset_phy_clk_n
dll_reference_clk
reset_request_n
local_init_done
local_rdata[]
local_rdata_error
Signal Name
Input
Input
Direction
Output
Output
Output
Output
Output
Output
Output
User control of the power-down feature. If Enable Power Down Controls
option is enabled, you can request that the controller place the memory
devices into a power-down state as soon as it can without violating the relevant
timing parameters and responds by asserting the local_powerdn_ack
signal. You can hold the memory in the power-down state by keeping this
signal asserted. The controller brings the memory out of the power-down state
to issue periodic auto-refresh commands to the memory at the appropriate
interval if you hold it in the power-down state. You can release the memory
from the power-down state at any time by deasserting the
local_powerdn_ack signal once it has successfully brought the memory out
of the power-down state.
option is enabled, you can request that the controller place the memory
devices into a self-refresh state by asserting this signal. The controller places
the memory in the self-refresh state as soon as it can without violating the
relevant timing parameters and responds by asserting the
local_self_rfsh_ack signal. You can hold the memory in the self-refresh
state by keeping this signal asserted. You can release the memory from the
self-refresh state at any time by deasserting the local_self_rfsh_req
signal and the controller responds by deasserting the
local__self_rfsh_ack signal once it has successfully brought the memory
out of the self-refresh state.
The system clock that the ALTMEMPHY megafunction provides to the user. All
user inputs to and outputs from the DDR HPC must be synchronous to this
clock.
The reset signal that the ALTMEMPHY megafunction provides to the user. It is
asserted asynchronously and deasserted synchronously to phy_clk clock
domain.
Reference clock to feed to an externally instantiated DLL.
Reset request output that indicates when the PLL outputs are not locked. Use
this signal as a reset request input to any system-level reset controller you
may have. This signal is always low when the PLL is trying to lock, and so any
reset logic using it is advised to detect a reset request on a falling edge rather
than by level detection.
When the memory initialization, training, and calibration are complete, the
ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the
memory controller, which then asserts this signal to indicate that the memory
interface is ready to be used.
Read and write requests are still accepted before local_init_done is
asserted, however they are not issued to the memory until it is safe to do so.
This signal does not indicate that the calibration is successful. To find out if the
calibration is successful, look for the calibration signal, ctl_cal_success or
ctl_cal_fail.
Read data bus. The width of local_rdata is four times the memory data bus.
Asserted if the current read data has an error. This signal is only available if the
Enable error detection and correction logic is turned on.
User control of the self-refresh feature. If Enable Self-Refresh Controls
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Description
External Memory Interface Handbook Volume 3
6–19