IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 86

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–34
Figure 5–17. Word-Aligned Writes
Notes to
(1) To show the even alignment of ctl_cs_n, expand the signal (this convention applies for all other signals).
(2) The ctl_dqs_burst must go high one memory clock cycle before ctl_wdata_valid. Compare with the word-unaligned case.
(3) The ctl_wdata_valid is asserted two ctl_wlat controller clock (ctl_clk) cycles after chip select (ctl_cs_n) is asserted. The ctl_wlat
(4) Observe the ordering of write data (ctl_wdata). Compare this to data on the mem_dq signal.
(5) In all waveforms a command record is added that combines the memory pins ras_n, cas_n and we_n into the current command that is issued.
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
indicates the required write latency in the system. The value is determined during calibration and is dependant upon the relative delays in the
address and command path and the write datapath in both the PHY and the external DDR SDRAM subsystem. The controller must drive ctl_cs_n
and then wait ctl_wlat (two in this example) ctl_clks before driving ctl_wdata_valid.
This command is registered by the memory when chip select (mem_cs_n) is low. The important commands in the presented waveforms are WR
= write, ACT = activate.
ctl_wdata_valid
ctl_dqs_burst
mem_cs_n
Figure
command
(Note 5)
mem_dqs
ctl_cas_n
ctl_wdata
ctl_ras_n
ctl_we_n
mem_clk
mem_dq
ctl_cs_n
Memory
Interface
ctl_addr
ctl_wlat
ctl_clk
5–17:
11 11
11 11
11 11
00 00
2
01
00 00
00000000
00000000
00000000
00000000
ACT
ACT
00 00
(1)
11
10
03020100
01
( 2)
11
11
07060504
(3)
(4)
10
00
11
00
00
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Chapter 5: Functional Description—ALTMEMPHY
0020008
11
11
WR
11
December 2010 Altera Corporation
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PHY-to-Controller Interfaces
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