IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 23

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Generated Files
Table 2–2. ALTMEMPHY Generated Files (Part 2 of 2)
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 1 of 2)
December 2010 Altera Corporation
<variation_name>_alt_mem_phy.v
<variation_name>_bb.v/.cmp
<variation_name>_ddr_pins.tcl
<variation_name>_ddr_timing.sdc
<variation_name>_pin_assignments.tcl
<variation_name>_report_timing.tcl
<variation_name>_alt_mem_phy_ad
dr_cmd
<variation_name>_alt_mem_phy_cl
k_reset
<variation_name>_alt_mem_phy_dp
_io
<variation_name>_alt_mem_phy_mi
mic
<variation_name>_alt_mem_phy_oc
t_delay
<variation_name>_alt_mem_phy_po
stamble
<variation_name>_alt_mem_phy_re
ad_dp
Module Name
Table 2–3
<variation_name>_alt_mem_phy.v/.vhd file. A particular ALTMEMPHY variation
may or may not use any of the modules, depending on the memory standard that you
specify.
File Name
shows the modules that are instantiated in the
All ALTMEMPHY variations
All ALTMEMPHY variations
All ALTMEMPHY variations
DDR3 SDRAM ALTMEMPHY
variation
DDR3 SDRAM ALTMEMPHY
variation when dynamic OCT is
enabled.
DDR3 SDRAM ALTMEMPHY
variations
All ALTMEMPHY variations
(unused for Stratix III or
Stratix IV devices)
Usage
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Contains all modules of the ALTMEMPHY variation
except for the sequencer. This file is always in Verilog
HDL language regardless of the language you chose in
the MegaWizard Plug-In Manager. The DDR3 SDRAM
sequencer is included in the
<variation_name>_alt_mem_phy_seq.vhd file.
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
Contains procedures used in the
<variation_name>_ddr_timing.sdc and
<variation_name>_report_timing.tcl files.
Contains timing constraints for your ALTMEMPHY
variation.
Contains I/O standard, drive strength, output enable
grouping, DQ/DQS grouping, and termination
assignments for your ALTMEMPHY variation. If your
top-level design pin names do not match the default
pin names or a prefixed version, edit the assignments
in this file.
Script that reports timing for your ALTMEMPHY
variation during compilation.
Generates the address and command structures.
Instantiates PLL, DLL, and reset logic.
Generates the DQ, DQS, DM, and QVLD I/O pins.
Creates the VT tracking mechanism for DDR3
SDRAM PHYs.
Generates the proper delay and duration for the
OCT signals.
Generates the postamble enable and disable
scheme for DDR3 PHYs.
Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.
External Memory Interface Handbook Volume 3
Description
Description
2–7