IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 45

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
Table 3–8. Controller Settings (Part 3 of 3)
December 2010 Altera Corporation
Multiple controller clock
sharing
Local interface protocol
Parameter
Controller Architecture
Both
HPC
This option is only available in SOPC Builder Flow. Turn on to
allow one controller to use the Avalon clock from another
controller in the system that has a compatible PLL. This option
allows you to create SOPC Builder systems that have two or
more memory controllers that are synchronous to your master
logic.
Specifies the local side interface between the user logic and the
memory controller. The Avalon-MM interface allows you to
easily connect to other Avalon-MM peripherals.
The HPC II architecture supports only the Avalon-MM interface.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Description
3–17