IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 170

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

9–24
Figure 9–14. Write Operation for HPC II—Merging Writes
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
AFI Memory Interface
Mem Command[2:0]
afi_wdata_valid[1:0]
local_address[25:0]
AFI Command[2:0]
local_wdata[31:0]
mem_addr[13:0]
local_burstbegin
Local Interface
Controller - AFI
afi_dqs_burst[0]
afi_dqs_burst[1]
Half-Rate Write Operation (Merging Writes)
local_write_req
afi_wdata[31:0]
local_size[4:0]
afi_addr[27:0]
mem_cs_n[0]
mem_odt[1:0]
mem_ba[2:0]
mem_dq[7:0]
local_be[3:0]
afi_cs_n[3:0]
afi_wlat[4:0]
local_ready
afi_dm[3:0]
afi_ba[5:0]
mem_cke
mem_dqs
mem_dm
mem_clk
phy_clk
00000000
F
0000000
The following sequence corresponds with the numbered items in
1. The user logic asserts a local_write_req signal with a size of 2 and an address of
2. The controller issues the necessary memory command and address signals to the
3. The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY
4. The controller asserts the afi_dqs_burst signals to control the timing of the DQS
5. The ALTMEMPHY megafunction issues the write command, and sends the write
6. For transactions with a local size of two, the local_write_req and local_ready
0×0000F1C.
ALTMEMPHY megafunction for it to send to the memory device.
megafunction that valid write data and write data masks are present on the inputs
to the ALTMEMPHY megafunction.
signal that the ALTMEMPHY megafunction issues to the memory.
data and write DQS to the memory.
signals must be high for two clock cycles so that all the write data can be
transferred to the controller.
22222222 33333333
0000001
[1]
0000002
[2]
00000000
0000003
B
ACT
0000000
NOP
F
ACT
4001000 0000000 4021008
WR
[3]
B
NOP
NOP
F
WR
B
1000
WR
00000000 22222222 33333333
0000000
NOP
0000
NOP
F
1008
WR
0
3
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
00
NOP
0000
00000000
[5]
Chapter 9: Timing Diagrams
22
Figure
0
[4]
33
3
[6]
9–13:
00