IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 96

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–2
Figure 6–2. DDR3 SDRAM HPC Architecture Block Diagram
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Avalon-MM or Native
Slave Interface
Command FIFO Buffer
Write Data FIFO Buffer
f
Figure 6–2
The blocks in
For information on the Avalon interface, refer to
This FIFO buffer allows the controller to buffer up to four consecutive read or write
commands. It is built from logic elements, and stores the address, read or write flag,
and burst count information. If this FIFO buffer fills up, the local_ready signal to the
user is deasserted until the main state machine takes a command from the FIFO
buffer.
The write data FIFO buffer holds the write data from the user until the main state
machine can send it to the ALTMEMPHY megafunction, which does not have a write
data buffer. In the Avalon-MM interface mode, the user logic presents a write request,
address, burst count, and one or more beats of data. The write data beats are placed
into the FIFO buffer until they are needed. In the native interface mode, the user logic
presents a write request, address, and burst count. The controller then requests the
correct number of write data beats from the user via the local_wdata_req signal, and
the user logic must return the write data in the clock cycle after the write data request
signal.
This FIFO buffer is sized to be deeper than the command FIFO buffer to prevent it
from filling up and interrupting streaming writes.
Command
Write Data
FIFO
FIFO
shows a block diagram of the DDR3 SDRAM HPC architecture.
Figure 6–2 on page 6–2
Tracking Logic
Write Data
Timer
Logic
Main State
Machine
State Machine
Chapter 6: Functional Description—High-Performance Controller
are described in the following sections.
Initialization
Management
Bank
Logic
Avalon Interface
PHY Interface
Address and
Command
Decode
Logic
December 2010 Altera Corporation
Specifications.
Block Description
ALTMEMPHY
Interface