IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 8

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–2
Release Information
Device Family Support
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller. The megafunction is available as a stand-alone product or
can be used in conjunction with Altera high-performance memory controllers. When
using the ALTMEMPHY megafunction as a stand-alone product, use with either
custom or third-party controllers.
Table 1–1
with ALTMEMPHY IP.
Table 1–1. Release Information
Altera verifies that the current version of the Quartus
previous version of each MegaCore function. The
and Errata
compilation with MegaCore function versions older than one release. For information
about issues on the DDR3 SDRAM high-performance controller and
theALTMEMPHY megafunction in a particular Quartus II version, refer to the
Quartus II Software Release
The MegaCore function provides either final or preliminary support for target Altera
device families:
■
■
■
■
Version
Release Date
Ordering Codes
Product IDs
Vendor ID
Final support means the core is verified with final timing models for this device
family. The core meets all functional and timing requirements for the device family
and can be used in production designs.
Preliminary support means the core is verified with preliminary timing models
for this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.
HardCopy Compilation means the core is verified with final timing models for
the HardCopy
requirements for the device family and can be used in production designs.
HardCopy Companion means the core is verified with preliminary timing models
for the HardCopy companion device. The core meets all functional requirements,
but might still be undergoing timing analysis for HardCopy device family. It can
be used in production designs with caution.
provides information about this release of the DDR3 SDRAM Controller
report any exceptions to this verification. Altera does not verify
®
Item
device family. The core meets all functional and timing
Notes.
10.0
July 2010
IP-SDRAM/DDR3 (HPC)
IP-HPMCII (HPC II)
00C2 (DDR3 SDRAM)
00CO (ALTMEMPHY Megafunction)
6AF7
MegaCore IP Library Release Notes
®
II software compiles the
Description
December 2010 Altera Corporation
Chapter 1: About This IP
Release Information