IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 12

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–6
Table 1–4. Resource Utilization in Arria II GX Devices
Table 1–5. Resource Utilization in Stratix III and Stratix IV Devices
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
DDR3 SDRAM (without
leveling)
Note to
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory controller overhead is
DDR3 SDRAM
(400 MHz, without leveling
only)
DDR3 SDRAM
(400 MHz, with leveling only)
DDR3 SDRAM
(533 MHz with read and write
deskew, with leveling only)
Note to
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory controller overhead is
additional.
additional.
Table
Table
Memory Type
Memory Type
1–4:
1–5:
Rate
Rate
PHY
Half
PHY
Half
Memory
Memory
Width
Width
(Bits)
(Bits)
16
64
72
16
64
72
16
64
72
16
64
72
8
8
8
8
(Note 1)
Combinational
Combinational
ALUTS
ALUTS
1,431
1,481
1,797
1,874
1,359
1,426
1,783
1,871
3,724
4,192
6,835
7,182
4,098
4,614
7,297
7,641
(Note 1)
Logic Registers
Logic Registers
1,189
1,264
1,970
2,038
1,047
1,196
2,080
2,228
2,723
3,235
6,487
6,984
2,867
3,391
6,645
7,144
December 2010 Altera Corporation
Blocks
Chapter 1: About This IP
Blocks
M9K
M9K
12
13
2
4
1
1
1
1
2
2
5
5
2
2
5
5
Resource Utilization
Memory
Memory
ALUTs
ALUTs
320
360
160
640
720
160
640
720
18
22
40
80
80
80
2
2