IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 118

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–2
Block Description
Figure 7–1. DDR3 SDRAM HPC II Block Diagram
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1
■
■
■
You only can migrate your HPC designs to HPC II if you are using an Avalon-MM
interface.
Figure 7–1
The side-band signals differ slightly for HPC II. If you use these signals, you need
to perform the following steps.
■
■
Because HPC II only supports a specific memory burst length, you must update
the memory burst length to match the controller settings. For DDR3, HPC II
supports on-the-fly burst length in half-rate mode.
Because HPC II supports arbitrary user burst length ranging from of 1 to 64, you
can adjust the max_local_size value in HPC II. Adjusting the maximum local size
value changes the width of the local_size signal. The maximum local_size
signal value is 2
local_size signal width of 2.
local_powerdn_ack
local_self_rfsh_ack
local_self_rfsh_req
local_autopch_req
local_refresh_chip
local_refresh_req
You need to drive an additional active high signal, local_refresh_chip, to
control which chip to issue the user-refresh to.
local_powerdn_req
The user-manual power signal is no longer supported in HPC II. Instead, you
can select auto power-down on the Controller Settings tab in the MegaWizard
Plug-In Manager, and specify the desired time-out (n cyles) after which the
controller automatically powers down the memory.
local_refresh_ack
local_refresh_req
local_rdata_error
local_rdata_valid
local_burstbegin
csr_waitrequest
local_write_req
csr_rdata_valid
local_read_req
local_init_done
local_multicast
csr_write_req
csr_read_req
ecc_interrupt
shows the top-level block diagram of the DDR3 SDRAM HPC II.
local_wdata
local_ready
local_rdata
local_addr
csr_wdata
local_size
csr_rdata
csr_addr
local_be
n
–1
, where n is the width of the local_size signal. HPC has a fixed
Performance Controller II
DDR3 SDRAM High-
ALTMEMPHY
Megafunction
Control
Logic
Chapter 7: Functional Description—High-Performance Controller II
mem_addr
mem_ac_parity
mem_ba
mem_cas_n
mem_cke
mem_cs_n
mem_dm
mem_odt
mem_ras_n
mem_we_n
parity_error_n
mem_dq
mem_dqs
mem_dqs_n
mem_err_out_n
December 2010 Altera Corporation
Block Description