IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 121

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Block Description
December 2010 Altera Corporation
Timer Logic
Command-Issuing State Machine
Address and Command Decode Logic
Write and Read Datapath, and Write Data Timing Logic
1
The timer logic models the internal behavior of each bank in the memory interface
and provides status output signals to the state machine. The state machine then
decides whether to issue the look-ahead bank management command based on the
timer status signals.
The command-issuing state machine decides what DDR commands to issue based on
the inputs from the command queue, bank management logic, and timer logic. The
DDR3 SDRAM provides half-rate command-issuing state machine. The half-rate state
machine supports 2T address and command, and issues “on-the-fly” memory bursts.
A longer memory burst length, in this case 8 beats, increases the command bandwidth
by allowing more data cycles for the same amount of command cycles. A longer
memory burst length also provides more command cycles that ensures a more
effective look-ahead bank management. However, longer memory burst lengths are
less efficient if the bursts you issue do not provide enough data to fill the burst.
This state machine accepts any local burst count of 1 to 64. The built-in burst adapter
in this state machine maps the local burst count to the most efficient memory burst.
The state machine also supports reads and writes that start on non-aligned memory
burst boundary addresses. For effective command bus bandwidth, this state machine
supports additive latency which issues reads and writes immediately after the ACT
command. This state machine accepts additive latency values greater or equal to t
– 1, in clock cycle unit (t
When the main state machine issues a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these signals into
AFI-specific commands and address. This block generates the following signals:
■
■
The write and read datapath, and the write data timing logic generate the AFI read
and write control signals.
When the state machine issues a write command to the memory, the IP core gets the
write data for that write burst from the write data FIFO buffer. The relationship
between the write command and write data depends on the afi_wlat signal. The
write data timing logic presents the write data FIFO read request signal so that the
data arrives on the external memory interface DQ pins at the correct time.
During write, the following AFI signals are generated based on the state machine
outputs and the afi_wlat signal:
■
Clock enable and reset signals: afi_cke, afi_rst_n
Command and address signals: afi_cs_n, afi_ba, afi_addr, afi_ras_n,
afi_cas_n, afi_we_n
afi_dqs_burst
CK
).
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
RCD
7–5