IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 114

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–20
Table 6–13. Local Interface Signals (Part 4 of 4)
Table 6–14. DDR3 SDRAM Interface Signals
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
local_rdata_valid
local_ready
local_refresh_ack
local_wdata_req
local_powerdn_ack
local_self_rfsh_ack
mem_dq[]
mem_dqs[]
mem_clk
mem_clk_n
mem_a[]
mem_ba[]
mem_cas_n
mem_cke[]
mem_cs_n[]
mem_dm[]
mem_odt[]
mem_ras_n
mem_reset_n
mem_we_n
Note to
(1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT)
I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses.
Signal Name
Table
Signal Name
(1)
6–14:
(1)
Table 6–14
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Direction
Output
Output
Output
Output
shows the DDR3 SDRAM interface signals.
Memory data bus. This bus is half the width of the local read and write data
busses.
Memory data strobe signal, which writes data into the DDR3 SDRAM and
captures read data into the Altera device.
Clock for the memory device.
Inverted clock for the memory device.
Memory address bus.
Memory bank address bus.
Memory column address strobe signal.
Memory clock enable signals.
Memory chip select signals.
Memory data mask signal, which masks individual bytes during writes.
Memory on-die termination control signal.
Memory row address strobe signal.
Memory reset signal.
Memory write enable signal.
Read data valid signal. The local_rdata_valid signal indicates that valid
data is present on the read data bus. The timing of local_rdata_valid is
automatically adjusted to cope with your choice of resynchronization and
pipelining options.
The local_ready signal indicates that the DDR3 SDRAM HPC is ready to
accept request signals. If local_ready is asserted in the clock cycle that a
read or write request is asserted, that request has been accepted. The
local_ready signal is deasserted to indicate that the DDR3 SDRAM HPC
cannot accept any more requests. The controller is able to buffer four read or
write requests.
Refresh request acknowledge, which is asserted for one clock cycle every time
a refresh is issued. Even if the Enable User Auto-Refresh Controls option is
not selected, local_refresh_ack still indicates to the local interface that the
controller has just issued a refresh command.
Write data request signal, which indicates to the local interface that it should
present valid write data on the next clock edge. This signal is only required
when the controller is operating in Native interface mode.
Power-down request acknowledge signal. This signal is asserted and
deasserted in response to the local_powerdn_req signal from the user.
Self refresh request acknowledge signal. This signal is asserted and
deasserted in response to the local_self_rfsh_req signal from the user.
Chapter 6: Functional Description—High-Performance Controller
Description
Description
December 2010 Altera Corporation
Top-level Signals Description