IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 73

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–10. DDR3 SDRAM Data Capture and Read Data Mapping in Stratix IV and Stratix III Devices
December 2010 Altera Corporation
mem_dqsn
mem_dqs
mem_dq
Figure 5–10
frequency at which the read data is handled.
Data Capture, Resynchronization, and Demultiplexing
The IOE in Stratix III and Stratix IV devices performs the following tasks during read
operation:
■
■
■
This operation is performed by feeding the resynchronized data into the HDR
conversion block within the IOE, which is clocked by the half-rate resynchronization
clock (resync_clk_1x). The resync_clk_1x signal is generated from the I/O clock
divider module, based on the resync_clk_2x signal from the PLL.
Read Data Storage Logic
The read block performs the following two tasks:
■
■
Postamble Protection
A dedicated postamble register controls the gating of the shifted DQS signal that
clocks the DQ input registers at the end of a read operation. This ensures that any
glitches on the DQS input signals at the end of the read postamble time do not cause
erroneous data to be captured as a result of postamble glitches.
Data Capture, Resynchronization,
and Data Demultiplexing
Captures the data
Resynchronizes the captured data from the DQS domain to the resynchronization
clock (resync_clk_1x) domain
Converts the resynchronized data into HDR data
Transfers the captured read data (rdata[n]_1x) from the half-rate
resynchronization clock (resync_clk_1x) domain to the half-rate system clock
(phy_clk_1x) domain using DPRAM. Resynchronized data from the DPRAM is
shown as ram_data_1x.
Reorders the resynchronized data (ram_rdata_1x) into ctl_mem_rdata, to be
presented in the user clock domain in the same clock cycle.
IOE
shows the order of the functions performed by the read datapath and the
dio_rdata1_1x
dio_rdata3_1x
dio_rdata2_1x
dio_rdata0_1x
resync_clk_1x
4n bits
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
wr_data
wr_clk
Read Datapath
Dual Port RAM
rd_data
rd_clk
External Memory Interface Handbook Volume 3
ram_rdata_1x[4n]
Mapping
Data
Logic
phy_clk_1x
ctl_rdata[4n]
5–21