IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 173

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The user logic requests the first write by asserting the local_write_req signal, and
2. The user logic initiates the first read to the same address as the first write. The
3. The user logic asserts a second local_write_req signal with a size of 1 and
4. The user logic asserts a second local_read_req signal with a size of 1 and address
5. The controller issues the necessary memory command and address signals to the
6. The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY
7. The controller asserts the afi_dqs_burst signals to control the timing of the DQS
8. The controller issues the first read memory command and address signals to the
9. The controller asserts the afi_doing_rd signal to indicate to the ALTMEMPHY
10. The ALTMEMPHY megafunction issues the write command, and sends the write
11. The ALTMEMPHY megafunction issues the first read command to the memory
12. The ALTMEMPHY megafunction returns the first data read to the controller after
the size and address for this write. In this example, the request is a burst length of
1 to a local address 0x000002. This local address is mapped to the following
memory address in half-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×0002<<2 = 0×0008
mem_bank_address = 0×00
request for the read is a burst length of 1. The controller continues to accept
commands until the command queue is full. When the command queue is full, the
controller deasserts the local_ready signal. The starting local address 0x000002 is
mapped to the following memory address in half-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×0002<<2 = 0×0008
mem_bank_address = 0×00
address of 0x000004.
of 0x000004.
ALTMEMPHY megafunction for it to send to the memory device.
megafunction that valid write data and write data masks are present on the inputs
to the ALTMEMPHY megafunction.
signals that the ALTMEMPHY megafunction issues to the memory.
ALTMEMPHY megafunction for it to send to the memory device.
megafunction the number of clock cycles of read data it must expect for the first
read. The ALTMEMPHY megafunction uses the afi_doing_rd signal to enable its
capture registers for the expected duration of memory burst.
data and write DQS to the memory.
and captures the read data from the memory.
resynchronizing the data to the phy_clk domain, by asserting the
afi_rdata_valid signal when there is valid read data on the afi_rdata bus.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–15:
9–27