IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 115

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
December 2010 Altera Corporation
Table 6–15
Table 6–15. ECC Logic Signals
ecc_addr[]
ecc_be[]
ecc_read_req
ecc_wdata[]
ecc_write_req
ecc_interrupt
ecc_rdata[]
Signal Name
shows the ECC logic signals.
Direction
Output
Output
Input
Input
Input
Input
Input
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Address for ECC logic.
ECC logic byte enable.
Read request for ECC logic.
ECC logic write data.
Write request for ECC logic.
Interrupt from ECC logic.
Return data from ECC logic.
External Memory Interface Handbook Volume 3
Description
6–21