IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 24

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–8
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Table 2–4. Controller Generated Files—All High-Performance Controllers
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
<variation_name>_alt_mem_phy_re
ad_dp_group
<variation_name>_alt_mem_phy_rd
ata_valid
<variation_name>_alt_mem_phy_se
q_wrapper
<variation_name>_alt_mem_phy_wr
ite_dp
<variation name>.bsf
<variation name>.html
<variation name>.v or .vhd
<variation name>.qip
<variation name>.ppf
<variation name>_example_driver.v or .vhd
<variation name>_example_top.v or .vhd
<variation_name>_pin_assignments.tcl
Module Name
1
Table 2–4
high-performance controllers, that may be in your project directory. The names and
types of files specified in the MegaWizard Plug-In Manager report vary based on
whether you created your design with VHDL or Verilog HDL.
In addition to the files in
the ALTMEMPHY files in
<variation_name>_alt_mem_phy_delay.vhd becomes
<variation_name>_phy_alt_mem_phy_delay.vhd.
Filename
through
DDR3 SDRAM ALTMEMPHY
variations (Stratix III and
Stratix IV devices only)
DDR3 SDRAM ALTMEMPHY
variations
All ALTMEMPHY variations
All ALTMEMPHY variations
Table 2–6
Usage
Table 2–4
Table
show the additional files generated by the
Quartus II symbol file for the MegaCore function variation. You
can use this file in the Quartus II block diagram editor.
MegaCore function report file.
A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the
Quartus II software.
Contains Quartus II project information for your MegaCore
function variations.
XML file that describes the MegaCore pin attributes to the
Quartus II Pin Planner. MegaCore pin attributes include pin
direction, location, I/O standard assignments, and drive
strength. If you launch IP Toolbench outside of the Pin Planner
application, you must explicitly load this file to use Pin Planner.
Example self-checking test generator that matches your
variation.
Example top-level design file that you should set as your
Quartus II project top level. Instantiates the example driver and
the controller.
Contains I/O standard, drive strength, output enable grouping,
and termination assignments for your ALTMEMPHY variation.
If your top-level design pin names do not match the default pin
names or a prefixed version, edit the assignments in this file.
2–2, but with a _phy prefix. For example,
through
A per DQS group version of
<variation_name>_alt_mem_phy_read_dp.
Generates read data valid signal to sequencer and
controller.
Generates sequencer for DDR3 SDRAM.
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
Table
2–6, the MegaWizard also generates
Description
Description
December 2010 Altera Corporation
Chapter 2: Getting Started
Generated Files