IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 33

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–3. DDR3 SDRAM Attributes Settings (Part 1 of 2)
December 2010 Altera Corporation
Output clock pairs from FPGA
Total Memory chip selects
Memory interface DQ width
Mirror addressing
Register Control Word 0–15
for Registered DIMMs
Memory vendor
Memory format
Maximum memory frequency
Column address width
Parameter Name
Table 3–3
memory attributes, initialization options, and timing parameters.
Samsung, Hynix,
See the memory
device datasheet
Discrete Device,
Elpida, JEDEC,
Nanya, other
through
1, 2, 4, or 8
Unbuffered
Range
Micron,
4–288
DIMM
10–12
1–6
—
—
(1)
Table 3–5
Units
pairs
MHz
bits
bits
bits
bits
—
—
—
describe the DDR3 SDRAM parameters available for
Defines the number of differential clock pairs driven from
the FPGA to the memory. Memory clock pins use the
signal splitter feature in Arria II GX, Stratix III, and
Stratix IV devices for differential signaling.
The ALTMEMPHY parameter editor displays an error on
the bottom of the window if you choose more than one
for DDR3 SDRAM interfaces.
Sets the number of chip selects in your memory
interface. The number of chip selects defines the depth of
your memory. You are limited to the range shown as the
local side binary encodes the chip select address.
Defines the total number of DQ pins on the memory
interface. If you are interfacing with multiple devices,
multiply the number of devices with the number of DQ
pins per device. Even though the GUI allows you to
choose 288-bit DQ width, DDR3 SDRAM variations are
only supported up to 80-bit width due to restrictions in
the board layout which affects timing at higher data
width. Furthermore, the interface data width is limited by
the number of pins on the device. For best performance,
have the whole interface on one side of the device.
On multiple rank DDR3 SDRAM DIMMs address signals
are routed differently to each rank; referred to in the
JEDEC specification as address mirroring.
Enter ranks with mirrored addresses in this field. There is
one bit per chip select. For example, for four chip selects,
enter 1011 to mirror the address on chip select #3, #1,
and #0.
Register Control Word values for the DDR3 registered
DIMMs. The values are available in the memory data
sheet of the respective registered DIMMs.
Lists the name of the memory vendor for all supported
memory standards.
Specifies whether you are interfacing with devices or
modules. SODIMM and MicroDIMM are supported under
unbuffered DIMMs. The ALTMEMPHY megafunction for
DDR3 SDRAM interfaces does not support registered
DIMM format. Arria II GX devices only support DDR3
SDRAM components without leveling, for example,
Discrete Device memory format.
Sets the maximum frequency supported by the memory.
Defines the number of column address bits for your
interface.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Description
3–5