IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 105

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Block Description
Table 6–4. ECC Registers (Part 2 of 3)
December 2010 Altera Corporation
Last or first double-bit error
error address
Last single-bit error error
data
Last single-bit error
syndrome
Last double-bit error error
data
Interrupt status register
Interrupt mask register
Name
Address
06
07
08
09
0A
0B
(Bits)
Size
32
32
32
32
5
5
Attribute
WO
RO
RO
RO
RO
RO
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
00000000
00000000
00000000
00000000
00000000
00000001
Default
This status register stores the last
double-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
This status register stores the last
single-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N-deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
This status register stores the last
single-bit error syndrome, which
specifies the location of the error bit on a
64-bit data word. As the data word is an
Nth multiple of 64, the syndrome is
stored in a N deep, 8-bit wide FIFO buffer
where each syndrome represents errors
in every 64-bit part of the data word. The
register gets updated with the correct
syndrome depending on which part of the
data word is shown on the last single-bit
error error data register. It can be cleared
individually by using the control word
clear.
This status register stores the last
double-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
This status register stores the interrupt
status in four fields (refer to
These status bits can be cleared by
writing a 1 in the respective locations.
This register stores the interrupt mask in
four fields (refer to
External Memory Interface Handbook Volume 3
Description
Table
6–7).
Table
6–6).
6–11