IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 151

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The local read request signal is asserted.
2. The controller accepts the request, the local_ready signal is asserted.
3. The controller asserts the ctl_doing_rd to tell the PHY how many clock cycles of
4. The read command (RD) on the command bus.
5. The mem_dqs signal has the read data from the controller.
6. These are the data to the controller with the valid signal.
7. The controller returns the valid read data to the user logic by asserting the
read data to expect.
local_rdata_valid signal when there is valid local read data.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–3:
9–5