IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 102

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Interrupts
The ECC logic issues an interrupt signal when one of the following scenarios occurs:
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■
The error counters increment every time the respective event occurs for all N parts of
the return data word. This incremented value is compared with the maximum
threshold and an interrupt signal is sent when the value is equal to the maximum
threshold. The ECC logic clears the interrupts when you write a 1 to the respective
status register. You can mask the interrupts from either of the counters using the
control word.
Partial Writes
The ECC logic supports partial writes. Along with the address, data, and burst
signals, the Avalon-MM interface also supports a signal vector that is responsible for
byte-enable. Every bit of this signal vector represents a byte on the data-bus. Thus, a 0
on any of these bits is a signal for the controller not to write to that particular
location—a partial write.
For partial writes, the ECC logic performs the following steps:
1. The ECC logic stalls further read or write commands from the Avalon-MM
2. It simultaneously sends a self-generated read command, for the partial write
3. Upon receiving the returned read data from the memory controller for the
4. The ECC logic merges the corrected or correct dataword with the incoming
5. The ECC logic sends the updated dataword to the encoder for encoding, and then
6. The ECC logic stops stalling the commands from the Avalon-MM interface so that
The following corner cases can occur:
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■
The single-bit error counter reaches the set maximum single-bit error threshold
value.
The double-bit error counter reaches the set maximum double-bit error threshold
value.
interface when it receives a partial write condition.
address, to the memory controller.
particular address, the decoder decodes the data, checks for errors, and then sends
it to the ECC logic.
information.
sends updated dataword to the memory controller with a write command.
the logic can receive new commands.
A single-bit error during the read phase of the read-modify-write process. In this
case, the single-bit error is corrected first, the single-bit error counter is
incremented and then a partial write is performed to this corrected decoded data
word.
A double-bit error during the read phase of the read-modify-write process. In this
case, the double-bit error counter is incremented and an interrupt is sent through
the Avalon-MM interface. The new write word is written to the memory location.
A separate field in the interrupt status register highlights this condition.
Chapter 6: Functional Description—High-Performance Controller
December 2010 Altera Corporation
Block Description