IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 100

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–6
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
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Figure 6–3
Figure 6–3. ECC Block Diagram
The ECC comprises the following blocks:
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Latency:
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Detects and corrects all single-bit errors. Also the ECC logic sends an interrupt
when the user-defined threshold for a single-bit error is reached.
Detects all double-bit errors. Also, the ECC logic counts the number of double-bit
errors and sends an interrupt when the user-define threshold for double-bit error
is reached.
Accepts partial writes
Creates forced errors to check the functioning of the ECC logic
Powers up to a ready state
The encoder—encodes the 64-bit message to a 72-bit codeword
The decoder-corrector—decodes and corrects the 72-bit codeword if possible
Maximum of 1 or 2 clock delay during writes
Minimum 1 or 3 clock delay during reads
shows the ECC block diagram.
Local Interface
To and From
From Local
To Local
Interface
Interface
N x 64 Bits
Message
N x 64 Bits
Message
Write
32 Bits
Read
Controller
Decoder-
Corrector
Encoder
ECC
ECC
Chapter 6: Functional Description—High-Performance Controller
N x 72 Bits
Codeword
N x 72 Bits
Codeword
Write
Read
Controller
Memory
N x 72 Bits
December 2010 Altera Corporation
DDR or DDR2
SDRAM
Block Description