IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 59

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–4. DDR3 SDRAM Unbuffered Module Clock Topology
December 2010 Altera Corporation
DDR3 SDRAM With Leveling
1
DQS/DQ
The mimic path in Arria II GX, Stratix III and Stratix IV devices is similar to
Figure
register; mem_clk_n[0] is generated by signal splitter.
Figure 5–3. Mimic Path
The calibration process for the DDR3 SDRAM PHY (with leveling) assumes an
interface in an unbuffered DIMM format, where the clock uses a fly-by termination,
refer to
With fly-by termination, each DDR3 SDRAM device on the DIMM sees the CK/CKn
edges at different times. Therefore, the sequencer must adjust the clock to launch the
DQS/DQSn and DQ signals so that it is appropriately aligned to the CK/CKn signals
on each device.
The DDR3 SDRAM leveling sequencer during calibration writes to the following
locations:
DQS/DQ
5–3. The only difference is that the mem_clk[0] pin is generated by DDIO
Figure
combout
mem_clk[0]
5–4.
DQS/DQ
mimic_data_in
measure_clk
DQS/DQ
CK/CK#
alt_mem_phy_mimic
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
DQS/DQ
ddiodatain
datain
outclk
DQS/DQ
External Memory Interface Handbook Volume 3
1
0
mem_clk_2x
DQS/DQ
measure_clk
DQS/DQ
ALTPLL
5–7